The subject matter disclosed herein relates generally to integrated circuits. More specifically, the disclosure provided herein relates to methods for reducing power consumption during a manufacturing test of an integrated circuit.
Power consumption of an integrated circuit during manufacturing test may be significantly higher than power consumption during functional operation. This is because functional modules of the chip that ordinarily do not work together during operation may be tested simultaneously. Moreover, a large number of flip-flops switch during a scan operation of a manufacturing test, when random values are moved through scan chains. Power consumption during scans has been shown to be several times higher during the test response capture cycle. A common solution to reduce power during the scans is to scan values into the chip at a slower rate. However, the slow rate of scanning will increase the time required to complete the test.
During an at-speed structural test (ASST), only one functional clock domain is tested at a time to prevent unpredictable asynchronous captures across clock domain boundaries. Even though only a fraction of the test pattern bits are used to test a single clock domain in a test pattern, data is scanned into all the flip-flops in the circuit. This represents a significant amount of power consumption during the test. To prevent yield loss because of higher power consumption during ASST, scanning has to be done at slower speeds. The time of ASST increases because of the cumulative effect of separate sets of slower scan operations needed for testing each functional clock domain.